This invention was made with Government support under contract awarded by the Government. The Government has certain rights in this invention.
1. Field of the Invention
The present invention relates to circuits useful in processing the output of image sensing arrays. More specifically, the present invention relates to Time Delay Integration (xe2x80x9cTDIxe2x80x9d) circuits usefull in processing the output of image sensing arrays.
2. Description of the Related Art
While Time Delay Integration (xe2x80x9cTDIxe2x80x9d) architecture is typically found in high speed digital image sensing devices such as Charge Coupled Device (xe2x80x9cCCDxe2x80x9d) image sensors to achieve satisfactory sensitivity, it has utility with many various types of image sensing arrays variously sensitive to, for example, the infrared, visible light, and X-ray wavelengths. In the TDI architecture, the image sensing array is optically scanned so that each part of the image is sensed with different parts, typically lines, of the array in a synchronized, delayed manner. The plural outputs over time of the image sensing array for each part of the image are summed, thereby improving the sensitivity and spatial resolution of the image sensing device. One measure of performance of image sensing devices is the Modulation Transfer Function (xe2x80x9cMTFxe2x80x9d), which is defined as the ratio of the modulation of the output signal to the modulation of the input signal, versus spatial frequency.
Typically, the TDI circuits are implemented in a type of silicon-based integrated circuit known as a Read-Out Integrated Circuit (xe2x80x9cROICxe2x80x9d), which is combined with the sensing array to form a Sensor Chip Assembly (xe2x80x9cSCAxe2x80x9d). SCAs are used in a variety of digital imaging systems, including, for example, night vision cameras, surveillance cameras, remote imaging cameras, and manufacturing line inspection cameras, and are suitable even for standard army dewar assembly (xe2x80x9cSADAxe2x80x9d) type applications and three color activities. Three color activities are scanning systems which incorporate more than one spectral band, or color, on a SCA. Each of the colors is defined by a bank of sensing elements on which a single spectral color is incident. SCAs are particularly useful when the sensing array is made of a non-silicon semiconductor material, which is typical since non-silicon semiconductor materials are inherently sensitive to various useful portions of the electromagnetic spectrum. Image information in the form of electrical charge is produced in the imaging array. The charge is collected and processed by the typically silicon-based ROIC. SCAs are manufactured using a variety of well known techniques, ranging from fabricating the sensing array separately from the ROIC and mounting the sensing array and ROIC on a common substrate or a common printed circuit board, to mounting the sensing array substrate on the ROIC substrate and then fabricating the sensing array.
Time delay integration may be performed in a SCA TDI architecture using a CCD array in a xe2x80x9cside riderxe2x80x9d configuration. Unfortunately, the design rules used for the integrated circuit do not allow for placing large storage wells and the other elements of the circuit in the unit cell for small unit cell areas, thereby limiting the maximum resolution of the CCD sensing device. While time delay integration can also be implemented using standard bucket brigade (xe2x80x9cBBDxe2x80x9d) circuits instead of CCDs, a need exists in the art for a TDI circuit that is useful in processing the output of image sensing arrays and has reduced ROIC circuitry relative to the ROIC circuitry required in the side rider CCD implementation while maintaining or improving MTF.
The need in the art is addressed by the present invention, which in one embodiment is a time delay integration circuit for acquiring a number n of samples per dwell. The time delay integration circuit comprises a plurality of first capacitors; a plurality of imaging sensor unit cell inputs controllably coupled respectively to the first capacitors; a plurality of groups of n second capacitors; and a plurality n of charge transfer paths comprising transfer gates coupled in series through path segments, the path segments of the charge transfer paths being coupled in succession to, alternately, one of the first capacitors and to respective second capacitors in one of the groups of second capacitors.
Another embodiment of the invention is a time delay integration circuit comprising a plurality of first capacitors; a plurality of imaging sensor unit cell inputs controllably coupled respectively to the first capacitors; a plurality of reset inputs controllably coupled respectively to the first capacitors; a plurality of second capacitors; a plurality of third capacitors; a first charge transfer path comprising a plurality of first transfer gates coupled in series through a plurality of first path segments, the first path segments being coupled alternately to respective ones of the first and second capacitors; and a second charge transfer path comprising a plurality of second transfer gates coupled in series through a plurality of second path segments, the second path segments being coupled alternately to respective ones of the first and third capacitors.
Another embodiment of the invention is a sensor chip assembly time delay integration circuit comprising a plurality of successively coupled circuit groups. Each of the circuit groups comprises a first phase clock node; a second phase clock node; a reset node; a unit cell input circuit; a first capacitor having a first plate coupled to the second phase clock node and a second plate; a switch having first and second terminals and a pole terminal, the first terminal being coupled to the reset node, the second terminal being coupled to the unit cell input circuit, and the pole terminal being coupled to the second plate of the first capacitor; a first transfer gate having a first terminal coupled to the second plate of the first capacitor and a second terminal; a second transfer gate having a first terminal coupled to the second plate of the first capacitor and a second terminal; a third transfer gate having a first terminal coupled to the second plate of the first capacitor and a second terminal; a fourth transfer gate having a first terminal coupled to the second plate of the first capacitor and a second terminal; a second capacitor having a first plate coupled to the first phase clock node and a second plate coupled to the second terminal of the fourth transfer gate; and a third capacitor having a first plate coupled to the first phase clock node and a second plate coupled to the second terminal of the third transfer gate. The second terminal of the first transfer gate and the second terminal of the third transfer gate of respective adjacent ones of the circuit groups are coupled together, and the second terminal of the second transfer gate and the second terminal of the fourth transfer gate of respective adjacent ones of the circuit groups are coupled together.
Another embodiment of the present invention is a method of time delay integration of image sensor charges, comprising storing accumulated image sensor charges from alternate sensor lines on respectively a plurality of first capacitors and a plurality of second capacitors; resetting a plurality of third capacitors; receiving a first set of image sensor charges on the third capacitors; transferring charge from the first capacitors respectively to the third capacitors through a set of first transfer gates, wherein charge is accumulated on the third capacitors; transferring charge from the third capacitors respectively to the first capacitors through a set of second transfer gates; resetting the third capacitors; receiving a second set of image sensor charges on the third capacitors; transferring charge from the second capacitors respectively to the third capacitors through a set of third transfer gates, wherein charge is accumulated on the third capacitors; and transferring charge from the third capacitors respectively to the second capacitors through a set of fourth transfer gates.